THE IMPROVEMENT OF TEST INDEPENDENCE FROM CIRCUIT REALIZATION

Abstract

We consider the possibilities of supplementing or expanding a particular realization test having a purpose to enhance test quality for detecting various defects. We suggest complementing the existing test suites of the IP core with sensitive adjacent patterns. Then the suitable test patterns for the synthesized gate level implementation have to be selected on the base of the fault simulation. Our experiments prove that such a complement would enhance the test quality for any synthesized IP core gate level description. We believe that the practice of sensitive adjacent patterns is a very cheap way to adopt test patterns for the re-synthesized gate level description of IP core, because the fault simulation is not so critical task as a test generation.