Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit

Authors

  • Lukas Sekanina Brno University of Technology, Faculty of Information Technology
  • Richard Ruzicka Brno University of Technology, Faculty of Information Technology
  • Zdenek Vasicek Brno University of Technology, Faculty of Information Technology
  • Vaclav Simek Brno University of Technology, Faculty of Information Technology
  • Petr Hanacek Brno University of Technology, Faculty of Information Technology

DOI:

https://doi.org/10.5755/j01.itc.42.1.925

Keywords:

Unclonable ID, Polymorphic Gate, Process Variation, Reconfigurable Circuit

Abstract

A unique unclonable chip ID has been implemented using various platforms in the recent years. In this paper, we investigate the use of polymorphic gates as a new mechanism for implementing a unique chip ID in systems already containing some polymorphic gates. The proposed solution exploits the fact that switching time of polymorphic gates (controlled by Vdd) is slightly different even for neighboring gates on the same die because of fabrication variations. We applied a partial reconfiguration in order to generate 48-bit IDs on the reconfigurable polymorphic REPOMO32 chip that we have developed in our previous research. We achieved 94.44% stable bits which is reasonably close to existing approaches.

DOI: http://dx.doi.org/10.5755/j01.itc.42.1.925

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Published

2013-02-07

Issue

Vol. 42 No. 1 (2013)

Section

Articles

License

Copyright terms are indicated in the Republic of Lithuania Law on Copyright and Related Rights, Articles 4-37.